1. Field of the Invention
The present invention relates to an operational amplifier. More particularly, the present invention relates to a pipeline circuit having a common operational amplifier.
2. Description of Related Art
Conventionally, in a variety of electronic circuits, the pipeline circuit is generally adopted for processing signals of each stage. In some of the pipeline circuits, an operational amplifier circuit is provided for each stage circuit to gain the corresponding signal respectively. Therefore, each operational amplifier circuit is only used in some specific period of time otherwise remains idle. Hereinafter, an image sensor will be illustrated as an example.
In recent years, image capture function or device is built in a variety of electronic appliances, especially mobile device such as mobile phone, personal digital assistant (PDA) or even toy. The specification of the image capture device is dependent on the electronic appliances. For the mobile device, a low power consumption and high definition image sensor is required for the image capture device. FIG. 1A is a schematic block diagram illustrating a conventional image sensor. Referring to FIG. 1A, a conventional image sensor includes a pixel array 110, row driver and voltage generator 120, sample and hold column circuit 130, gain circuit 140 and analog/digital (A/D) converter 150. The row driver and voltage generator 120 provides a plurality of driving signals of rows 121, a plurality of reference voltages 122 and a reference voltage VCL. The driving signals of rows 121 are received by the corresponding electrodes (not shown) of the pixel array 110 respectively. The image is sensed by the pixel array, and then a plurality of pixel signals of columns 111 are outputted according to the timing of the driving signals of rows 121. The pixel signals of columns 111 are received, sampled and held sample by the hold column circuit 130. Then, the pixel signals are arranged in cascade to generate a pixel signal 131. The pixel signal 131 is received and amplified by the gain circuit 140 to generate a pixel signal 141. The A/D converter circuit 150 generally includes a pipeline A/D converter circuit, wherein the analog pixel signal 141 is converted into a digital pixel signal 151 according to the reference voltages 122. The digital pixel signal 151 is outputted to the successive circuit (e.g., the control logic circuit 160 shown in FIG. 1).
Generally, in the image sensor of FIG. 1A, the gain circuit 140 and the A/D converter circuit 150 have pipeline structure. FIG. 1B is a circuit diagram illustrating a conventional pipeline gain circuit. Referring to FIG. 1B, the gain circuit 140 of FIG. 1A including a pre-stage gain block 142 and a post-stage gain block 143 is illustrated. Each stage of gain blocks includes a sample circuit 144 or 146 and an amplifier circuit 145 or 147 respectively. Therefore, the signal is sampled and held in the sample circuit, and then is gained by the amplifier circuit. For example, the pixel signal 131 is amplified by the gain circuit 140, the pre-stage gain block 142 is set at a sampling phase (or represented as a reset phase), thus the pixel signal 131 is held in the capacitors C1 and C2. At this moment, the post-stage gain block 143 is set at a gain phase, the pixel signal 148 held in the capacitors C5 and C6 is provided by the sample circuit 146 and gained by the operational amplifier circuit OP2 to output a pixel signal 141. In other words, referring to the circuit diagram illustrated in FIG. 1B, the sense switches SW1 to SW6 are turned on and the sense switches SW7 to SW12 are turned off. At this moment, the operational amplifier circuit OP1 is idle. After the pixel signal 131 is sampled and held by the sample circuit 144 of the pre-stage gain block 142, the pre-stage gain block 142 is set at gain phase. The pixel signal 131 provided by the sample circuit 146 is gained by the pixel signal 148 via operational amplifier circuit OP1 and outputted. At this moment, the post-stage gain block 143 is set at reset phase, and the pixel signal 148 is sampled and held. In other words, referring to the circuit diagram illustrated in FIG. 1B, the sense switches SW1 to SW6 are turned off and the sense switches SW7 to SW12 are turned on. At this moment, the operational amplifier circuit OP2 is idle. By repeating the steps described above, the pixel signal 131 is gained to be a pixel signal 141 and outputted by the gain circuit 140.
Accordingly, it is noted that, when the operational amplifier circuit OP1 is used, the operational amplifier circuit OP2 is idle, and vice versa (i.e., when the operational amplifier circuit OP2 is used, the operational amplifier circuit OP1 is idle). Generally, in order to maintain the gain of the operational amplifier at high level, a specific DC power is adopted for the operational amplifier. Therefore, in an analog circuit, the amplifier consumes more power. For example, pipeline analog digital converter and pipeline gain circuit are adopted for a complementary metal oxide semiconductor (CMOS) transistor image sensor. Therefore, each stage of the CMOS image sensor includes an operational amplifier circuit. However, in the timing of sample and hold of the circuit, the operational amplifier circuits are only operated about every half-period, thus, about half-period of power is consumed. Therefore, the power is consumed due to the idling of the operational amplifier circuits. Furthermore, the area and cost of the circuit is increased since in the pipeline circuit, each stage circuit includes an operational amplifier circuit.